Is it okay to leave the MOSFET body as a floating node?

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paragt1026

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When designing an adder using the TSMC 65nm model, is it okay to leave the body as a floating node without connecting to the source, VDD, or VSS?
 

It is OK using the 97nm. But 65 or even 130 - not OK. Read the manual.
 

I wouldn't, unless you are trying to make something like
a GGNMOS clamp where you -want- snapback. Maybe
some study says some node is OK but generally, tie it off.

What upside do you imagine? One less route in the layout?
 

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