Is it necessary to resynchronize the reset here?

[jan2008]

in my design, PLL and clock divider are reset by rstn, clock divider is connected to PLL output, clk_a/clk_b/clk_c are generated by clock divider. Should I use rstn directly for modules clocked by clk_a/clk_b/clk_c, or resynchronize rstn with clk_a/clk_b/clk_c, producing rstn_a/rstn_b/rstn_c and use them for modules clocked by the corresponding clock? when should reset resynchronization be used?

 

[archillios]

I think you still need reset synchronization. The rstn is not guaranteed to be synchronized to PLL output clock.

 

[raul_777_h]

I think the problem is how width the rstn plus is. There are several cases:
1. the rstn voilated for recovery or removal time.
2. Even if reset synchrinized. if the plus is too narrow, the clk_a/clk_b/clk_a can't sample it.

Thus, i think you should make sure the rstn plus is wide enough.