Is it a huge barrier from FPGA to ASIC world?

[maizzz]

I've been a IP engineer in the FPGA field for over 10 years. Lately I had an interview in an EDA company and was told that everything is OK but lacking of ASIC flow experience is a big risk.

Personally I want to enter the ASIC world, but how could I open a Gate of the ASIC world if all the "ASIC" companies always need someone has "ASIC" experience?

Very frustrated.

 

[FvM]

Without rating the interviewer's viewpoint about big risk in this regard, I would suggest to learn about ASIC design. So you are able to answer related questions, show that you are aware of difference's in design methodology and give the impression that you're able to cope with new challenges.

This won't help if the interviewer is primarly looking for "intelligent apes" who are used to operate a specific ASIC design tool, but surely if he's assessing problem solving capability.