Hi,
I have a doubt regarding GLS. We are designing a very large complex SOC now we are running GLS but since SOC is very complex, compilation and elaboration are taking 6-7 hours. So, It is very difficult to do the GLS in this case.
Is only STA timing closure is enough here? what you guys say on this? Has Anyone some suggestions what to do here?
I am a strong advocate of GLS; especially the simulation of scan chains post clock tree synthesis.
If you understand every warning from RTL lint and synthesis check_design AND have not used any synthesis directives to "help" guide synthesis, I would still recommend at least some GLS.
It is always recommended to do a GLS before you tape out an ASIC due to the following reasons:
1) Any wrong timing exceptions (false path,MCP etc) set during synthesis can be caught in GLS
2) Can ensure there are no initial value dependency for the flops
3) synthesis tools have the limitation that they cannot analyze the asynchronous boundaries well.
4) Also it gives some amount of confidence that your design will work on silicon