Is FPGA process sequential?

[mashhur]

Dear readers,

I am confusing about how FPGA works.
I am S/W developer and I know C/C++/C# like these programming languages believe sequential process. You can easily find out when you debug step by step your code. But I dont have any idea about FPGA once after I saw the code below:

always@(posedge 100mhz)
begin
read_prev0 <= PIN13;
read_prev1 <= read_prev0;

if(read_prev1 && ~read_prev0)
read_sync <= 1'b1;
else
read_sync <= 1'b0;
end

There is only comment written is in order to synchronize the CPU with FPGA, the read enable(read_sync) is used.
So, if we discuss this code sequence if PIN13 reaches "1", read_prev1 and read_prev0 are always "1" and read_sync is always "0". So from this point read enable never gets "1" because of "IF STATEMENT = if(read_prev1 && ~read_prev0)" and code doesnt make sense.

I might be wrong on it because my brain is only able to realize sequential code.
If I am wrong or any further comments please share them up. I would appreciate your all ideas.
Thanks!

 

[cwjcwjcwj]

No, it is not sequential. They work in parallel and they are digital hardware (not like C++/C).

Search for RTL to understand how FPGA works. There are millions of tutorial on internet.

 

[TrickyDicky]

What will really confuse you will be when you read about all the sequential parts of HDL languages.

 

[std_match]

I want to point out that the code is not correct if the signal at PIN13 is asynchronous to the clock.
One more register stage is needed. First two register stages for synchronization, then one additional stage for edge detection.

 

[TrickyDicky]

I want to point out that the code is not correct if the signal at PIN13 is asynchronous to the clock.
One more register stage is needed. First two register stages for synchronization, then one additional stage for edge detection.

Just being pedantic, the code is correct, but the design is wrong as you suggested.