Is DRC rule: Metal3 overlapping with VIA2 necessary?

[helpless]

DRC Rule for Metal3/VIA2

Is the DRC rule : Metal3 overlapping with VIA2 necessary. What will happen if there is a VIA2 but no Metal3 on top of it in a triple metal layer process. Any potential problem will arise as a result of this?

 

[flyankh]

Re: DRC Rule for Metal3/VIA2

Hi,helpless
I think this situation will not happen in a real case.If you needn't let M2 to M3,the VIA2 is not necessary too.




cheers,
flyankh.

 

[zouwanghui]

Re: DRC Rule for Metal3/VIA2

Is the DRC rule : Metal3 overlapping with VIA2 necessary. What will happen if there is a VIA2 but no Metal3 on top of it in a triple metal layer process. Any potential problem will arise as a result of this?

I dont think it is necessary! but why you make VIA2 without M2-to-M3 connection?

 

[helpless]

Re: DRC Rule for Metal3/VIA2

I was just wondering what will the "VIA2" material after you fabricate it.
Will it still be METAL3?

 

[flyankh]

Re: DRC Rule for Metal3/VIA2

The VIA2 in the physical layout is just a hole between the metal2 layer and the metal3 layer.It is not belonged to metal2 or metal3.Actually,the VIA2 is an independent layer

 

[cyrabbit]

Re: DRC Rule for Metal3/VIA2

I was just wondering what will the "VIA2" material after you fabricate it.
Will it still be METAL3?

Yes, it will be fill by Metal3

 

[uncle_urfi]

Re: DRC Rule for Metal3/VIA2

If you have a sea of VIA2s but no metal3 on top, then you run the risk of creating antennas. This is usually covered by the DRC rules under the "antenna errors" category.
This is not a warning, but an error (at least in the processes that i know, like TSMC, Motorola, STBicmos, Sige-ibm and the like)
and you cannot tape-out your chips until these are removed.

 

[uladz55]

Re: DRC Rule for Metal3/VIA2

Hi,

I think it's depend on your process.
If you fill VIA hole with refractory metall (for ex. W), it's not very dengerous if you miss Me3 over VIA2.
When you will etch Me3 you can only slightly etch refractory metall, but not Me2.

Antenna effect occurs when big open surface of floating conductive layers connect to gate oxide.

regards,

Uladz55

 

[uladz55]

Re: DRC Rule for Metal3/VIA2

something else about antenna effect.

Usually it's dangerous for thin gate oxide.
TSMC consider this effect for 0.25u, 0.18u,... process.

Metall and Poly layers (conductive layers) "collect" charges.

Total area of coductive layer is not so important, the most critical is the side area because only this side area collect charges during plasma etching.

Diffusion regions are source - drain regions.
So, if you have very long conductive line, connected to small area of gate oxide (for ex. you connect output and input of inverters ) better to connect this line to source-drain region first (by CONTACT) and after that connect to gate (by VIA).

b/rgds

 

[Fom]

Re: DRC Rule for Metal3/VIA2

If you have only single contact and it is not overlapping according to design rules metal in VIA hole will be etching in case of any mask misalignment. As a result the contact in this place will be not reliable.

 

[Hughes]

Re: DRC Rule for Metal3/VIA2

Is the DRC rule : Metal3 overlapping with VIA2 necessary. What will happen if there is a VIA2 but no Metal3 on top of it in a triple metal layer process. Any potential problem will arise as a result of this?

Even though no physical or electrical problems, leaving VIA2 uncovered by Metal3 is not a good design, because those VIA2's are reduntant objects.

 

[xinsu]

Re: DRC Rule for Metal3/VIA2

It is a DRC error.
In general, via cell include bottom metal ,top metal and via layer,so you'd better use via cell not draw the via layer seperately to avoide this error.

 

[omsi]

DRC Rule for Metal3/VIA2

drc error.

it shows minimum metal3 area