Is the DRC rule : Metal3 overlapping with VIA2 necessary. What will happen if there is a VIA2 but no Metal3 on top of it in a triple metal layer process. Any potential problem will arise as a result of this?
Is the DRC rule : Metal3 overlapping with VIA2 necessary. What will happen if there is a VIA2 but no Metal3 on top of it in a triple metal layer process. Any potential problem will arise as a result of this?
I dont think it is necessary! but why you make VIA2 without M2-to-M3 connection?
The VIA2 in the physical layout is just a hole between the metal2 layer and the metal3 layer.It is not belonged to metal2 or metal3.Actually,the VIA2 is an independent layer
If you have a sea of VIA2s but no metal3 on top, then you run the risk of creating antennas. This is usually covered by the DRC rules under the "antenna errors" category.
This is not a warning, but an error (at least in the processes that i know, like TSMC, Motorola, STBicmos, Sige-ibm and the like)
and you cannot tape-out your chips until these are removed.
I think it's depend on your process.
If you fill VIA hole with refractory metall (for ex. W), it's not very dengerous if you miss Me3 over VIA2.
When you will etch Me3 you can only slightly etch refractory metall, but not Me2.
Antenna effect occurs when big open surface of floating conductive layers connect to gate oxide.
Usually it's dangerous for thin gate oxide.
TSMC consider this effect for 0.25u, 0.18u,... process.
Metall and Poly layers (conductive layers) "collect" charges.
Total area of coductive layer is not so important, the most critical is the side area because only this side area collect charges during plasma etching.
Diffusion regions are source - drain regions.
So, if you have very long conductive line, connected to small area of gate oxide (for ex. you connect output and input of inverters ) better to connect this line to source-drain region first (by CONTACT) and after that connect to gate (by VIA).
If you have only single contact and it is not overlapping according to design rules metal in VIA hole will be etching in case of any mask misalignment. As a result the contact in this place will be not reliable.
Is the DRC rule : Metal3 overlapping with VIA2 necessary. What will happen if there is a VIA2 but no Metal3 on top of it in a triple metal layer process. Any potential problem will arise as a result of this?
It is a DRC error.
In general, via cell include bottom metal ,top metal and via layer,so you'd better use via cell not draw the via layer seperately to avoide this error.