is always@(posedge clk) similar to rising_edge(clk)??

brunokasimin · Oct 22, 2008

always @(posedge clk)

hello,

is always@(posedge clk) similar to rising_edge(clk)??

thx

tkbits · Oct 23, 2008

Re: always @(posedge clk)

very similar.

Async set and clear are also listed as edge signals. The difference is whether or not the signal appears in a condition in the always block.

Code:

always @(posedge clk or posedge rst)
begin
  if (rst)          // listed signal used here, has priority
    do <= 8'h5A;    // constants only for async set and async clear
  else              // clk not mentioned
    do <= di;       // sync updates, by clk
end

brunokasimin · Oct 23, 2008

Re: always @(posedge clk)

hello,

for example, here is a verilog code:

always @(posedge clk)
begin
err <= 0;
if (ce && (addr[0] || addr[1]))
err <= 1;
end

so, i can write a vhdl code here like this:

elsif rising_edge(clk) then
err <= '0';
if(ce && (addr(0) or addr(1))) then
err <='1';
end if;
end if;

Comments are really appreciated

is always@(posedge clk) similar to rising_edge(clk)??

brunokasimin

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tkbits

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brunokasimin

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is always@(posedge clk) similar to rising_edge(clk)??

brunokasimin

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tkbits

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