If the complaint is "timestep too small" then look for a
couple of things.
One is device models which are "too ideal" or "too simple",
lacking capacitances especially, which allows insane node
movement and let solution "get out over its skis" and unable
to back-step (this is wht timestepping fails, it cannot go back
further than the last accepted (even if, or especially if wrongly)
timepoint.
Another is, there's a default behavior for initial timestep. It
is possible that, if you have sources whose "activity rate" is
higher than 1/(tstop/1000) your analysis might entirely miss
an event (or worse, only miss part of its effects and catch
others, resulting in a kind of matrix cognitive dissonance
that could only have been resolved at the time but now is
baked in until solution gives up). So anyway, be sure that
your declared timestep is smaller than your smallest declared
stimulus risetime (which should be smaller than PW and so on).
You might try replacing those IC behaviorals with sources
just for debug, because behavioral models tend to embed
the kinds of too-ideal elements and blind states, which defy
initialization or develop insane intermediate solutions that
blow up instead of converge. If you think it's the FET, take
out everything but the right hand third of the schematic and
make HO, LO be roughly-right pulsed sources. If the problem
is still there, at least you've cut the "location fog" by 2/3.
Swap in somebody else's FET, maybe that "fixes" things.
On and on until it gets on its feet.