IP verilog file in Quartus format , wish change to Xilinx format

[lgeorge123]

I have five verilog IP file in Quartus NIOS II format , and wish change them to in Xilinx IP format , the most difficult part is lcd_buffer.v which is involved in Avalon part , As I am not familiar with Xilinx , can someone help me change them to Xilinx format ?





https://www.cnblogs.com/Neddy/archive/2011/04/25/2026774.html

 

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I doubt you're going to get any volunteers to help change them for you (unless you're willing to pay them).

So instead how about taking the opportunity to learn some useful bus protocols:
Avalon interface: https://www.altera.com/literature/manual/mnl_avalon_spec.pdf
Xilinx AXI4 (ARM/AMBA) Interface:
https://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf
https://www.arm.com/products/system-ip/amba/amba-open-specifications.php

In fact learning the AXI4 is probably more useful than knowing Avalon (which is Altera only).

When you get stuck with your code modifications post the code you've done (on this forum, no links) and a description of the problem and any testbench you're using and you'll surely get a better response (than one that tells you to go make an effort to enhance your knowledge).


Regards

 

[lgeorge123]

Thanks your help !!