IO ports and Physical pins in a FPGA - Spartan6

[graphene]

Does the number of IO ports mean the number of physical pins available on a FPGA device? I want to use Spartan6 FPGA and I am able to seen only few tens of pins in the device. Can someone share your ideas ? Thanks in advance.

Also in the product description I see Maximum Single-Ended Pins = 480and Maximum Differential Pairs = 240.. what does this mean ?

 

[ads-ee]

IO pins are the pins that you can define on the device (user pins). The number of physical pins will be much higher as they will include power, ground, configuration, and other miscellaneous pins. Have no idea what you mean by "I am able to seen only few tens of pins in the device"

Single ended are pins that can be input or output or bidirectional but only use one pin. Differential pairs send/receive signals to the device using two pins. The signals on the two pins look like signals inverted from each other. The difference between them is what a differential receiver "sees". To get more information on differential signals google "LVDS" which is a popular differential standard that is used a lot.

Regards

 

[graphene]

When i see the Spartan 6 placed in a PCB, adding all the pins in the 4 sides of the device, I am hardly able to see 40-50 pins ... I am not understanding how does it count to 150 or 200 pins .. please share your ideas..
.
my sincere thanks to you for clarifying me with the above answers... was really helpful..

 

[TrickyDicky]

Of those 200 pins, probably 25-50% of them will be ground and power supply. The others will include things like configuration pins. When all these are taken away that leaves you with 50 pins for user logic.

 

[graphene]

Thank you a lot ..

I have another question. so other than understanding what is a CLB and what are slices, how effective shall that be for me to think in terms of describing my design in an FPGA?
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Anyways, I shall test the functionality of my design with my simulation and synthesis and how effective shall that be with the knowledge of undertanding CLB, SLices and I/O pins ?

 

[TrickyDicky]

It depends how you're designing. Usually, you dont write code at the CLB/slice level. Thats what the synthesisor is for.
Aslong as you stick with the design templates and do synchronous design you should be fine. IO pin mapping is only needed at the fit stage, not the functionality stage.

 

[graphene]

thank you trickydicky and thank you all .... was really helpful..

 

[ads-ee]

Adding to Tricky's post. You might want to think about how many inputs any given register requires to implement the combinatorial logic in front of your synchronous registers. This will determine the number of LUTs that are required and the levels of logic you'll have between registers in the implemented design.

E.g. suppose you want to compare two 64-bit values at 500 MHz using a part with 6-input LUTs, as you can only compare 3-bits from each value in 1 LUT you'll need more than 1 level of logic to do the comparison, which means that you are most likely going to have to write the behavioral code as a pipelined compare.

Regards

 

[graphene]

so does it mean while describing my hardware in HDL, I need to code them as in to compare 3 bits from each input at a time and then sum up the logics ... or does the synthesiszer does this for us as said by a friend above?

 

[ads-ee]

The synthesis tool should take care of that but coding something like this might result in a lot of combinational logic (enough to violate setup time).

---

Code Verilog - [expand]
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module test (
input clk,
input a_pin, b_pin,
output reg c_pin
);
 
reg [63:0] a, b;
reg  c;
 
always @ (posedge clk) begin
  a <= a_pin;
  b <= b_pin;
  c <= (a == b) ? 1'b1 : 1'b0;
  c_pin <= c;
end
 
endmodule

---

Looks very simple from a behavioral view, but if you consider how that comparison logic gets mapped into LUTs then you'll find that there are a lot of levels of logic (LUTs). The above code should compile so you can try this out on your own in ISE/Vivado/QuartusII web versions and take a look at the implementation schematic.

Regars