Hi,
I am a student working with AMS Hit-Kit V4.0 for a digital IC design.
I have simulated the pre-layout netlist with NCVerilog and found the simulation was fine.
But the post-layout simulation, which includes the Input and Output pads, shows the input signals fed into the INPUT PAD comes out on the other side of the PAD with the switching noise added to it. The attached shows this. audio_in[7:0] is the input fed into the pad and audio_in_nopad[7:0] is what is see from the other side of these pad.
I am using FirstEncounter for the layout design and generated the *.sdf and verilog netlist from the layout design.
Can I get any help to know where I am going wrong and How to solve this problem?
Thank you.