Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

IO location for clock

Status
Not open for further replies.

maheyadav333

Member level 1
Joined
Oct 22, 2010
Messages
36
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,518
i have warning in plan ahead .


WARN: [HD-UCFReader 7] Clock terminal Clk is located on a non-clock IO location R8 this can produce sub-optimal results, line no : 6


where i should locate this clk
 

You should locate it on a package pin that is intended for a global clock. These pins are annotated with "GC", I beleive, in planAhead.

r.b.
 

if the board has already made ​​some sense to spend this clk transit through the crystal and connect straight to gclk pin. But not in altera
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top