Inverter configuration of CMOS over CS stage

[aryajur]

Common Source Stage

Why isn't the inverter configuration of CMOS preferred as an amplifier stage over a CS stage with current source load. The inverter configuration will provide much more gain. Is it just because the input will see nearly twice the input capacitance to the stage, or are there more reasons. If this is the only reason, why is it so widely used in digital?

 

[rambus_ddr]

Re: Common Source Stage

First, the inverter high is very depend on it's dc point.
second, the lineary of inverter is poor.

 

[terryssw]

Re: Common Source Stage

Inverter circuits can be used as an amplifier, and they usually be configured as Class-AB amplifier (or Class-B, depends on biasing conditions) since both PMOS and NMOS receive driving force from the inputs. However, Class-AB circuits are difficults to bias than the traditional Class-A circuits, since a floating constant voltage source must be presented between the gate of two MOSFET (If no such voltage source are used, i.e. the case of simple inverter circuits, the Class-AB amplifier can only works for very narrow range of VDD, Vthp and Vthn). While the tranditional Class-A ones used only active loads, a current mirror is enough for well biased it.

 

[radigital]

Re: Common Source Stage

It is possible to decrease the gain of a CMOS inverter, by
scaling of the PMOS and NMOS dimensions to enable its usage
as an amplifier, but you need to ensure that its input signal is
small enough under all conditions so that it will not overdrive the
inverter. Even then, you need some king of bias arrangement
to limit the current in the stage, so that the gain stays stable,
which again boils down to the requirement of using a current
mirror for bias.

--Radigital