introduce delay in a gate clock in SoC Encounter

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oAwad

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Hello all,

I want to introduce a special delay in clock signal for one gate in my layout design in SoC Encounter, is there a direct way to do it in SoC Encounter ?

* The design clock period is 2ns, while the delay that I want to introduce in the gate is 0.2ns
* The delay should be for this gate only not for the whole design.

if I increase the net length of the clock of that gate, can I achieve an 0.2ns delay ?

Thanks
 

It is really hard to get these fine-grained delays reliably. It's not a "digital" practice.
 

ThisIsNotSam said:
It is really hard to get these fine-grained delays reliably. It's not a "digital" practice.
Click to expand...

I know it would be hard, but can it be achieved by adding clock buffers to this special clock net ? ( to make use of the propagation delay of buffers)

In fact I'm working on interfacing an analog part with a digital design, so this is somehow a special net.
 


It is possible, but you have to understand that you can't create a precise delay of say 20ps. You will create a spread of say 10-30ps, because both the gates and the interconnect behave differently from corner to corner and from die to die.

If you can, I would push this delay gate to the analog block, where you can do all sorts of MC simulations and make sure it will work reliably.
 
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