Are you sure this was the question you were asked
Sure. This question is very practical and seems a famous one... Let's say you need to synthesize the Block-B, so that its timing would meet the connected blocks 'A' and 'C', which were already synthesized. Each of these blocks (A, B, and C) have got the timing budgets (see the timing requirements in the first post on this thread).
The set_input_delay and set_output_delay commands are needed to model the timing of your design in the context of the larger system
Sure, in respect to connected modules / signals. These commands actually define min/max delays on the timing paths of the considered design (design where the constraints are applied to).
I can see that this question is bothering you (multiple references in unrelated threads
Yes, it is. I hope that constraints, which I have put, they are correct. I would also like to receive some approvals from more experience engineers.
My concern on the input/output min delays (hold) definition. Are they correct?
By defining the input min delay for '-2', I want to force the tool to implement the min delay of 2ns on the Logic-2.
By defining the output min delay for '-1', I want to force the tool to implement the min delay of 1ns on the Logic-3.
Is that correct?
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negative input delay is a valid constraint: it just means that the data become stable before the clock edge
I interpretative this in another way: The data might be changed before the active clock edge (this way the data should be delayed against the clock internally inside of the cell).