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interview questions can anybody help me

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vlsitechnology

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How you can increase clock frequency?
What are multi-cycle paths? Give example?
What are the various timing-paths which should be taken care in STA?
What are delay models and difference between them?
On what basis do u decide a setup and hold time for a flip flop ??
 

carv_13

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I think pipelining can be used to increase clock frequency. There are many more methods like logic optimization.

Various timing paths would be Input to register, register to output, register to register and input to output.
 

csmode

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we have to give both importance,if u r specific u have to give hold as important.because if u have hold viol. left chip wont work,if u have setup u can decrease clk frec. to work.
 

vlsi_whiz

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Take a look the following PDF. It explains Multi-cycle paths and timing analysis.
 

vjm16

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Normally, when two flip-flops are connected in cascade, with some combinational logic in between and if we give an input at one clock edge, we expect the output in the next clock itself. In multicycle paths, this criteria does not meet. The output will be delayed by some number of clocks.
 

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