venkatgandham
Junior Member level 2
I have my interview day after tomorrow.
.
I am unable to ask myself questions based on booth multiplier and UART.
Can anybody ask me some questions based on this topics .
Details are as follows.
We designed a boothmultiplier using vhdl code and optimized its delay power and area using RTL compiler and SOC Encounter tools.
we just changed the parameters of the tool and able to reduce the delay,area and power. As far as I know we changed the floorplan and we got this results. Please based on this ask me some questions and also some other questions.
For low noise Amp,
Fc = 1.5ghz, Gain> 20db, Noise figure < 5 db, power dissipation<15 mw with Vdd=2.5v.
SPDR > 70db, CL=800f.
Uart designed using Vhdl code and tested by writing a testbench for T and R.
Please explain why the clk of receiver takes 16 times the baud rate?
The start bit begins.
2. At its next clock cycle, the receiver detects that the start bit has begun. This may be up to 1/16 of a bit period after the actual start.
3. After another 8 cycles, the receiver samples the line again. If the line is still at logic 0, the start bit is confirmed. Otherwise the initial transition is dismissed as noise.
4. After another 16 cycles the receiver samples the line. This is repeated a further 7 times, to get the values of the eight data bits.
My question is why it takes 16 clk cycles to get one data?
Please Help,
.
I am unable to ask myself questions based on booth multiplier and UART.
Can anybody ask me some questions based on this topics .
Details are as follows.
We designed a boothmultiplier using vhdl code and optimized its delay power and area using RTL compiler and SOC Encounter tools.
we just changed the parameters of the tool and able to reduce the delay,area and power. As far as I know we changed the floorplan and we got this results. Please based on this ask me some questions and also some other questions.
For low noise Amp,
Fc = 1.5ghz, Gain> 20db, Noise figure < 5 db, power dissipation<15 mw with Vdd=2.5v.
SPDR > 70db, CL=800f.
Uart designed using Vhdl code and tested by writing a testbench for T and R.
Please explain why the clk of receiver takes 16 times the baud rate?
The start bit begins.
2. At its next clock cycle, the receiver detects that the start bit has begun. This may be up to 1/16 of a bit period after the actual start.
3. After another 8 cycles, the receiver samples the line again. If the line is still at logic 0, the start bit is confirmed. Otherwise the initial transition is dismissed as noise.
4. After another 16 cycles the receiver samples the line. This is repeated a further 7 times, to get the values of the eight data bits.
My question is why it takes 16 clk cycles to get one data?
Please Help,
