Interview questions about digital CMOS

[rammohanvlsi]

1)exp various mosfet capacitance&their significance?
2)exp sizing of inverter.
3)give the expression for cmos switching power dissipation.
4)what happens to delay if u increase the load capacitance.
5)what happens if we increase the number of contacts or via from 1 metal layer to the next.
6)Draw a transistor level 2 i/p nand gate.explain it sizing (a)considering vth (b)for equal rise and fall times.
7)what is charge sharing?exp charge sharing problem while sampling data from a bus.
8)why dont we use just one nmos or pmos transistor as a transmission gate.
9)draw a 6-t sram cell and exp the read & write operation.
10)what is the critical path in a sram.

 

[no_mad]

digital cmos

Try this link:

**broken link removed**

Hope it helps.