Hi,
u know the time path model DC/PT will analyze is DFF'S CLOCK TO NEXT DFF'S DATA-IN.
in order to analysis the I/O timing path , assign a true clock or virtual clock for the I/O port, make the I/O analysis based the model like the above(DFF->DFF) .
Of course need use set_input_delay ,set_output_delay orders to constrain the path.
As sunjian was saying you know that there are 4 paths considered for performing STA
I-O,I-R,R-R,R-O
clock period and clock uncertainity are needed to time(or constrain) the R-R path
Input delay is needed to time(or constrain) the I-R path
Output delay is needed to time(or Constrain) the R-O path
The assignments are done through virtual clock or a true clock of adjacent block in the case of input and output delays.
Hi Guys,
When we talk of IO timing we all thing of Synchronous Interfacses (Ie I/F running wrt some clock).
Can we discuss on Asyncronous Intrefaces IO Timings.
We can start with a SDRAM access in Asychnronous mode. Any takers on the same or any pointers to tutorial, documents.