interview question on setup...please solve

[vlsi_maniac]

hi all,
1)Convert D-latch into divider by 2.
2)What is the max clock frequency the circuit can handle ?
T_setup= 6nS
T_hold = 2nS
T_propagation = 10nS

thanks

 

[raju3295]

1> connect Q! of the D-latch to D ,,Q output will wrk as div 2 of ck freq

2>can u elaborate the qn ,, if i assume that the u have mentioned the setup/hold vilations

chip will wrk at 1/12 units,, after the hold fix.

 

[vlsi_maniac]

can you please tell how you got 12ns
thanks

 

[TA37]

I figure min period is 16nS (max freq 62.5MHz):

At t=0, there is a clock edge. It will take 10nS for the value at D to propagate to Q and Q!. If you are connecting Q! directly to D, then D will see its value transition at t=10nS. Then you still have to wait another 6nS before the next clock edge or you have not given sufficient setup time at D.

Hold time is irrelevant for the calculation. Except that you have to confirm that hold > propagation or the circuit just won't work to begin with.

 

[raju3295]

sorry i was assuming that u have given the violation numbers,
now i got they r flop timings ..ok

i feel ,, propogation delay has no effect on this,, as launch and caputure are at the same flop, and u need to have 2 ns of logic delay to over come the hold effect , so total 8ns of delay in Q! to D path.. so i feel the freq should be 1/8 ns,

Am happy to discuss over it. and happy to see more messages on it

 

[senthilos]

Hi TA,

I believe you are trying to say hold <propagation so that the Q! signal stays stable at D input. Is that right?

I figure min period is 16nS (max freq 62.5MHz):

At t=0, there is a clock edge. It will take 10nS for the value at D to propagate to Q and Q!. If you are connecting Q! directly to D, then D will see its value transition at t=10nS. Then you still have to wait another 6nS before the next clock edge or you have not given sufficient setup time at D.

Hold time is irrelevant for the calculation. Except that you have to confirm that hold > propagation or the circuit just won't work to begin with.

 

[TA37]

Oops. Yeah, hold < propagation. 2< 10.

 

[denki23]

Assuming T_propagation is the clock-to-q delay and the "circuit" is just two flops connected directly with no combinational logic in between then:
T_min = T_setup + T_propagation = 16ns -> fmax = (1/16ns) = 62.5GHz
There's no hold violation because by the time our hold period is done, the previous stage still has 8 more ns to go before it appears at the output.

 

[raju3295]

yep, i got confused at hold, but am not able to agree with denki23 on setup, if i put everything in normal PT equations and assuming x is the clk period

Data arrival= 0+10+0=10 units (st time+propogation delay+combo delay)
Data required =x+10-6=x+4 units (nxt rise edge +propogation delay-setuptime)
for max freq it can run
x+4=10
x=6 units
so i arrive at 1/6 ns 166GHz

Any comments

 

[denki23]

I didn't notice this was a latch the first time through. So it's a latch with a 0 delay inverter between it's output and input. Then the pulsewidth of the transparent level needs to be at least Tclk-q (measured from the opening edge) + Tsetup (measured from the closing edge) and the opaque level can be no shorter than the hold time (measured after the closing edge). this gives Tclk = Thigh + T low = (Tclk-q + T-setup) + Thold = 10ns + 6ns + 2ns = 18ns. (1/18ns) = 55MHz. With %89 duty cycle.

Anybody agree? Disagree?

Added after 4 minutes:

also, my previous answer should have been 62.5MHz not GHz...