interview question on gate sizing

[cuttoncandy]

Hi, there is an interview question "consider a situation wherein the sizing of all gates is changed from 2:1 to 1.5:1.what would be the reason to change"
I think it's probably because the change of manufacturing but I couldn't figure out.
Thanks!

 

[srp8514]

Usually the P/N ratios are changed to modify the pull up or pull down strength for the cell.
In you case since the PMOS is being made weak that means there was a requirement for strong NMOS meaning cells having better 1->0 transition.
These type of modifications to P/N ratio are very common for cells being used on tight datapaths for certain processor applications.

Other reason might be reduced PN ratio means more compact cell design. This sizing might be better for the std cell design. You could save like a track or two per std cell. Thus making your design more compact. However this is achieved at the expense of a weak 0->1 transition time. Which could mean more leakage.

 

[Abhishek_BITSPilani]

The reason given by srp8514 looks promising. To reduce the area required by your gates, you will reduce the transistor sizes, at the expense of a weak 0 - 1 transition.

Another reason can be a change in the material used for transistor fabrication. It might change the carrier mobilities of p and n type materials (un and up), and hence to match the new ratio of un/up we would have to change our transistor sizes.

 

[Yanxiang Huang]

Gate down-sizing is a common trick when you have timing slacks.

It reduces W/L ratio, as L is constant, hence reduces cell area.

BTW, I also experienced reduced power consumption, we used to believe it is because of reduced area. But I am not sure where that comes from. Any idea?

 

[srp8514]

@Yanxiang
You might have seen a reduction in dynamic power.
Dynamic power = 0.5 * C * V^2 * F * (activity factor)
By reducing the gate size you are reducing the pin Cap.
Which could account for reducing the dynamic power.

 

[saurabhr8here]

Two possible reasons:

1. If the mobilities of PFET vs NFET is 2:1, then going for a size ratio of 1.5:1 would be to change the delay slopes of rising/falling transition.

2. For recent technologies, strain engineering enhanced the mobility of electrons and holes. However, PFET and NFET respond to different kinds of strain in different direction (compressive vs. tensile). Using epitaxial SiGe in the Source/Drain regions of the PFET, its possible to strain the channel so that the hole mobility is quite close to electron mobility. That'd be a big reason to change the PFET/NFET drive strength.