jayanth03
Newbie level 4
Design a black box whose input clock and output relationship as shown in attachment.
I think I know how do do it using HDL...
In Verilog: Output = repeat (2) @ (posedge clk) clk
Can some one please tell me how to design this using logic gates and FF's.
Thanks
Jayanth
I think I know how do do it using HDL...
In Verilog: Output = repeat (2) @ (posedge clk) clk
Can some one please tell me how to design this using logic gates and FF's.
Thanks
Jayanth