Dec 6, 2006 #1 J jayanth03 Newbie level 4 Joined Jul 21, 2006 Messages 7 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,335 Design a black box whose input clock and output relationship as shown in attachment. I think I know how do do it using HDL... In Verilog: Output = repeat (2) @ (posedge clk) clk Can some one please tell me how to design this using logic gates and FF's. Thanks Jayanth
Design a black box whose input clock and output relationship as shown in attachment. I think I know how do do it using HDL... In Verilog: Output = repeat (2) @ (posedge clk) clk Can some one please tell me how to design this using logic gates and FF's. Thanks Jayanth
Dec 7, 2006 #2 N nand_gates Advanced Member level 3 Joined Jul 19, 2004 Messages 899 Helped 175 Reputation 350 Reaction score 53 Trophy points 1,308 Activity points 7,037 This is the way! Code: +------------+ | | | +-----+ | +--|D Q|---|---+ | | | | _____ | | | +------| \ CLK | | | | )---- OUT ----+-----|> /Q|---+ +------|_____/ | +-----+ | | | | +------------+--+ | | | | | +-----+ | | +--|D Q| | | | | | | | | | | | | | +-----o|> /Q|---+ +-----+
This is the way! Code: +------------+ | | | +-----+ | +--|D Q|---|---+ | | | | _____ | | | +------| \ CLK | | | | )---- OUT ----+-----|> /Q|---+ +------|_____/ | +-----+ | | | | +------------+--+ | | | | | +-----+ | | +--|D Q| | | | | | | | | | | | | | +-----o|> /Q|---+ +-----+
Dec 7, 2006 #3 U user100 Newbie level 4 Joined Nov 8, 2006 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,309 Give D input to D filp flop --> xor of clk and Q(OUT)