hello all,i faced an interview yesterday and was stuck with one particular question of digital design.
the question is as design a Combinational logic which takes a train of pulses with different pulse width (1ns - 5ns) and produces pulses of only 5ns as output.it should discard pulse widths less than 5ns.
help appreciated.
I believe you can build a comb logic to monitor the input every 1ns and have a counter running. If for 5 consecutive sampling if the input is sensed as HIGH then the output should be driven HIGH for 5ns and reset the counter. Otherwise the output should be driven LOW and reset the counter.
Obviously the method I described above has a delay of 5ns from input to output as the system built is a causal system(i.e. input has to be observed completely before the output is driven. We can't make any assumption about the input in real time.)
Two latches, 1st latch has input data and enable is clock of 5ns, 2nd latch has input from out put of 1st latch and enable is inverted clock of 5ns.
see below figures
Be interested to know the answer...if there is one...
It would have to rely on combo delay, which would be very PVT sensitive would it not? I'm sure you could come up with a pulse-rejection cct, but how accurate to 5 ns it would be I don't know.
Unless it's a trick question where they want you to explain why such a cct would not be that reliable or accurate.