# interview qstn on comb ckt to remove less time pulse

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#### Guru59

##### Full Member level 4
hello all,i faced an interview yesterday and was stuck with one particular question of digital design.
the question is as design a Combinational logic which takes a train of pulses with different pulse width (1ns - 5ns) and produces pulses of only 5ns as output.it should discard pulse widths less than 5ns.
help appreciated.

i have attached a reference figure

#### tdminion

##### Member level 1
not combinational.....synchronous.

#### Guru59

##### Full Member level 4
No...the interviewers were keen to know a synthesizable combinatinal DUT

#### denki23

##### Junior Member level 3
can we use an RS latch?

#### senthilos

##### Newbie level 6
I believe you can build a comb logic to monitor the input every 1ns and have a counter running. If for 5 consecutive sampling if the input is sensed as HIGH then the output should be driven HIGH for 5ns and reset the counter. Otherwise the output should be driven LOW and reset the counter.

Obviously the method I described above has a delay of 5ns from input to output as the system built is a causal system(i.e. input has to be observed completely before the output is driven. We can't make any assumption about the input in real time.)

Any objections or good ideas?

#### Guru59

##### Full Member level 4
well i said combinational circuit...
how can counter be a combinational.....?

#### shitansh

##### Full Member level 5
Two latches, 1st latch has input data and enable is clock of 5ns, 2nd latch has input from out put of 1st latch and enable is inverted clock of 5ns.
see below figures

HTH

#### denki23

##### Junior Member level 3
shitansh, the question required a combinational circuit.

#### glb

##### Newbie level 6
Rely on gate capacitance to do RC filtering?

#### shitansh

##### Full Member level 5
denki23 said:
shitansh, the question required a combinational circuit.
Latch is combinational circuit, isn't it?

#### denki23

##### Junior Member level 3
i think a generally accepted definition of combinational logic is logic that doesn't maintain state, so a latch wouldn't count.

#### glb

##### Newbie level 6
Be interested to know the answer...if there is one...

It would have to rely on combo delay, which would be very PVT sensitive would it not? I'm sure you could come up with a pulse-rejection cct, but how accurate to 5 ns it would be I don't know.

Unless it's a trick question where they want you to explain why such a cct would not be that reliable or accurate.

#### sunilbudumuru

##### Full Member level 2
hi friends,

how abt the following combo ckt...?
very optimistic solution....

its a thought but need some development and discussion on this.

Sunil Budumuru

#### dcreddy1980

##### Full Member level 5
May be this circuit also gives the required solution. I have attached the picture.

Comment are welcome

#### research_vlsi

Design a Buffer with 5 ns inertial delay.

#### jitendravlsi

##### Full Member level 2
Dear Reddy,

are these ( 1ns, 2ns, 3ns, 4ns, 5ns ) delay buffers or something else?

Dear Sunil,
We can give a pulse of max 5ns but here you are giving a pulse of 6 ns to get output pulse of 5 ns.

can we play with number of levels(delay buffers and AND gates) to get proper output?

your approach is very good, but it need some modification.

thanks & regards
jit

#### dcreddy1980

##### Full Member level 5
Jitender,

Yes they are delay cells of size 1ns, 2ns, 3ns and so on

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