2) Once a clock to the flop is gated, is the 'Enable' signal to the FF still required (I understood it does, but I cannot understand why)
It does because, we can switch on and off the clk supply only with this enable pin.
3) Gated Clock - how it also might be used for power reduction besides its main purpose of gating the clock
Since it gates the clock, the total block will be inactive and hence no switching activity in the block -> reduced dynamic power.
4) Besides gating the clock and switching off the power, what another techniques are used for reduction of power consumption?
Multi VDD, multi threshold, architecture level low power method, power gating etc.