[Interview] Low Power Design Methodologies

[ivlsi]

Hi All,

Here are the interview questions related to Low Power Design:

1) What commands should be applied during a logic synthesis for insertion of the Gated Clocks in the Netlist?
2) Once a clock to the flop is gated, is the 'Enable' signal to the FF still required (I understood it does, but I cannot understand why)
3) Gated Clock - how it also might be used for power reduction besides its main purpose of gating the clock
4) Besides gating the clock and switching off the power, what another techniques are used for reduction of power consumption?

Thank you!

 

[sakthikumaran87]

2) Once a clock to the flop is gated, is the 'Enable' signal to the FF still required (I understood it does, but I cannot understand why)
It does because, we can switch on and off the clk supply only with this enable pin.
3) Gated Clock - how it also might be used for power reduction besides its main purpose of gating the clock
Since it gates the clock, the total block will be inactive and hence no switching activity in the block -> reduced dynamic power.
4) Besides gating the clock and switching off the power, what another techniques are used for reduction of power consumption?
Multi VDD, multi threshold, architecture level low power method, power gating etc.

 

[ivlsi]

we can switch on and off the clk supply only with this enable pin

I meant a situation where the same FF has a gated clock and also Enable signal. Is there a sense for this situation? Might the same signal be used as for a clock gating control as for Enable signal to the same Flop? Is there a sense?

 

[saurabhr8here]

DVFS: Dynamic Voltage and Frequency Scaling is a known method to reduce dynamic power. As sakthikumaran mentioned, using multi-Vt transistors depending on critical/non-critical paths can be another way to reduce power. However, balancing timing using mult-Vt transistors in a given design can be non-trivial.

 

[ivlsi]

balancing timing using mult-Vt transistors in a given design can be non-trivial.

Why? Each cell has deterministic delays, are not they? Why is do hard to close timing for Multi-Vt Cells?

 

[saurabhr8here]

The level of difficulty depends on how many process/temperature corners you need to validate your design. For example, temperature behavior of sub-45nm FETs has changed since Vdd-Vt is much smaller than before (Vt does not scale like before) and mobility and Vt have opposite temperature trends. Essentially, low Vt devices (with higher Vdd-Vt) behave like traditional FETs with high temperature as the slow corner, while high-Vt devices have low temperature as the slow corner. Hence, in a mixed Vt design, characterizing at the worst case corner becomes an issue and additional margining may be required.

 

[andy_freak]

2) Once a clock to the flop is gated, is the 'Enable' signal to the FF still required (I understood it does, but I cannot understand why
You don't need an enable signal going to the FF if the enable signal is used to gate the clock unless,
1) The enable signal is used for both the purposes, to update the signal going to flop and for gating the flop also.
always @ (posedge clk)
begin
if (a)
begin
c <= a + b;
end
end
In the above example "a" can be used to gate the clock going to "c" as well as for computing the value "a+b".
2) If the flop being gated is a synchronous reset flop. In that case reset is also an enable condition for clock gating and it goes to reset pin of gated flop also.

 

[layowblue]

Answer to 1): For RC: set_attribute lp_insert_clock_gating true
Answer to 2): Usually the synthesis tool understands the enable signal in RTL, and should translate it into ECK pin of the FGCG(Fine Grained Clock Gating).