I have internal and external violations in my design . By Internal I mean Reg to reg paths, By external I mean " Input pin to reg " and " reg to output pin " .
How to I go about fixing them ?? Should I remove my internal and external setup violations first and then fix hold ? Or should I fix both seupt and hold internally and then go to external violations ???
I have internal and external violations in my design . By Internal I mean Reg to reg paths, By external I mean " Input pin to reg " and " reg to output pin " .
How to I go about fixing them ?? Should I remove my internal and external setup violations first and then fix hold ? Or should I fix both seupt and hold internally and then go to external violations ???
I think you'd better fix R2R setup timing , then fix all hold timing for R2R , IO path.
Finally, you'd better clear all hold, if setup spec can not meet, you can slow down the clock frequency to meet.
For input to reg or reg to output violations, you should know if you have any timing constraint for this I/O.
If not, you could relax the I/O to/from reg timing.