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Interfacing VHDL design with a Verilog testbench

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orangelogic

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Hello,

I am working on asic project and I have a IP core in VHDL. Now, i need to write the verilog code for the testbench. can someone tell me how do I do this interfacing.

I understand that there has to be some wrapper around my VHDL design. But can someone throw more light on this. Thanks in advance....
 

sree205

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entity a ( input b : std_logic;
output c : std_logic);

architecture a1 of a

end architecture

module tb_a ();

wire b;
wire c;

a1 a (.b(b),
.c(c);


initial
begin
// test vectors here
end

endmodule


simplest example of mixed signal simulation. just write a verilog testbench considering vhdl entity as a verilog module and instantiate the vhdl entity in it. try to simulate the verilog file using modelsim. it should work.
 

gliss

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sree205 said:
simplest example of mixed signal simulation.

Just to be clear, that's not mixed signal, that's mixed language or mixed hdl simulation.
 

salma ali bakr

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can we also have a testbench in SystemVerilog for a design in VHDL and do the same as with a verilog testbench???
 

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