interfacing very high frequency ADC board question

[vahidkh6222]

virtex-6 adc ghz oscilloscope

hi,
i have an ADS5474 evaluation board. ACD is expected to work up to 400 MSMPS.
and i use another FPGA board (Virtex% sx95) with a high speed LVDS connector to interface the evaluation board. i also have an appropriate cable which according to datasheet must support up to 4 GHz data transfers.
but what i get is very boisy digital outputs from ADC.
here is bit diagram of one reading of low frequency sin waveform. as you may see on DATA_PORT(13), i.e. the sign bit, there are some glitches on this bit(also on other bits,but harder to see) that causes interference in original signal. what do you suggest the problem is?
is it bad termination, side effect of neighboring pathes or what?
any ideas?

 

[melc]

receiver adc ground connection

Your question is incomplete. How do you suppose someone will answer if you don't say nothing about how did you supplied the boards. There are many technique to minimise the noise. First is not clear if glitches are clock sincronised or not.
Then is not clear how do you use the A2D, single ended or differential. Then if you have a properly mounted differential cable between boards (for LVDS operation). Do you have a good common mode voltage on the A2d input? But the ground between boards... and so on.

 

[FvM]

high speed adc board

I expect, that the Virtex inputs are set to LVDS standard with internal differential termination and that a differential pair of the said "4 GHz cable" is connected for each bit? If so, there could be an issue of common mode interferences exceeding the common mode range. Dow you also have a low impedance ground connection with the cable?

 

[vahidkh6222]

fpga adc board

Your question is incomplete. How do you suppose someone will answer if you don't say nothing about how did you supplied the boards. .

I'm sorry; I did not know which specific details I should present.

There are many technique to minimize the noise. First is not clear if glitches are clock sincronised or not.

As you may have seen, many of the glitches occur in the middle of each consistent sign, i.e. we do not expect any change in the value but there exist a glitch. i conclude here that the glitches are not clock synchronous.(maybe wrong) and also we can see some simultaneous glitches between neighboring bits. One may conclude It's kind of a side effect. I'm not sure at all

Then is not clear how do you use the A2D, single ended or differential. Then if you have a properly mounted differential cable between boards (for LVDS operation). Do you have a good common mode voltage on the A2d input?

My A2D outputs are all differential pairs compatible with LVDS standard along with a differential LVDS DRY signal at half the rate of sampling. Common mode voltage is ok I think. but what do you mean by properly mounted connectors? I have used standard LVDS compatible cable and connectors...

But the ground between boards... and so on.

What about the grounds. I connect and disconnect the grounds of two boards but it did not make any differences.
I also tried delayed versions of DRY*2 to maximize setup time, but there were not a tiny difference with 10 to 350 degrees of phase differences.

 

[FvM]

fpga probe board adc

So everything is also O.K. at the receiver side? Then you shouldn't get the shown "spikes". Even a correct reference clock wouldn't be required at this point, cause the high bits can be expected as statical for a longer time, it would matter, when trying to receive consistent data words.

Im not familiar with Virtex LVDS receiver options, but I guess, it can be excluded that a possibly connected SERDES or dual-edge input register causes the spikes?

 

[vahidkh6222]

high frequency adc

I expect, that the Virtex inputs are set to LVDS standard with internal differential termination and that a differential pair of the said "4 GHz cable" is connected for each bit? If so, there could be an issue of common mode interferences exceeding the common mode range. Dow you also have a low impedance ground connection with the cable?

thanks for the response,
yes the Virtex inputs are set to LVDS standard and so,
but what do you mean by "low impedance ground connection with the cable"?!
i have connected all differential outputs of A2D and the DRY...but what about the ground!?

Added after 4 minutes:

So everything is also O.K. at the receiver side? Then you shouldn't get the shown "spikes". Even a correct reference clock wouldn't be required at this point, cause the high bits can be expected as statical for a longer time, it would matter, when trying to receive consistent data words.

Im not familiar with Virtex LVDS receiver options, but I guess, it can be excluded that a possibly connected SERDES or dual-edge input register causes the spikes?

I've check my FPGA board configuration and I'm sure about the reciever.
but I cant understand what the SERDES is. since DRY is at half rate(which means any rising and falling edges reperesent new data) , I multiply it's rateby an internal DLL in FPGA and use the rising edge of the double rated clk...

 

[FvM]

هل يعرف أحد adc له high frequency

You already mentioned, that you have common ground for both boards (as should be expected), so the common mode voltage at the input should be correct. Low impedance ground in my question meant, that a sufficient ground connection should be together with the LVDS pairs, not only e.g. through the power supply. Otherwise you possibly could get common mode interferences overloading the differential receivers. I don't think that this is likely to happen, but it could be. Normally a shield connected at both ends of the differential cable would achieve the said ground connection. But I don't know the exact situation with your eval boards, what kind of connectors are used, how the cable is attached to connectors?

To check the signal quality, you would need a high speed (>= 1 GHz) oscilloscope and a differential probe, if possible. Also with a single ended active probe, the signal quality could be checked roughly. Otherwise, ADS5474 sampling clock could be decreased as far as 20 MHz for test purposes, don't know if this can be achieved easily with the eval board.

Added after 9 minutes:

P.S.: A SERDES would normally be used with serialized LVDS data only, but with some FPGA families, it has to be connected when LVDS IO standard is used, although no deserialization is intended. It should work as you did.

 

[vahidkh6222]

high frequency adc

you mean there must be exist a geound connection, for every LVDS pair, right?
and I have blue ribon coaxial AWG38 cable and SAMTEC QSE connectors. is there any good document for learning this subjects?
i actually test the board on 100 meg. at 45 meg the results were good...
thanks for your help.

 

[FvM]

adc high frequency low power

Samtec provided cable assemblies for QSE/QTE have a signal ground, that connects to the QSE ground bar. Something similar would be good. Using two 50 ohms coaxial cables as with SATA is also O. K. with the outer conductor connected a both sides.

 

[melc]

adc samtec connector

It's still a question about the power supply.
The A2D has the option for different power supply for analogic and digital side. One way for good SNR is to keep the digital voltage lower than analog voltage, it that your situation? How long is the differential cable between the A2D board and FPGA board? Do you have a logic analyzer available in your lab? Could you check the output of A2D at the A2D evaluation board mictor connector (without any connection with the FPGA board) ?

 

[vahidkh6222]

adc 4ghz

problem solved,
there was a need for two 100ohm terminations at both ends of the cable in order to get clear signals...
thanks my friends for being helpful