هل يعر٠أØد adc له high frequency
You already mentioned, that you have common ground for both boards (as should be expected), so the common mode voltage at the input should be correct. Low impedance ground in my question meant, that a sufficient ground connection should be together with the LVDS pairs, not only e.g. through the power supply. Otherwise you possibly could get common mode interferences overloading the differential receivers. I don't think that this is likely to happen, but it could be. Normally a shield connected at both ends of the differential cable would achieve the said ground connection. But I don't know the exact situation with your eval boards, what kind of connectors are used, how the cable is attached to connectors?
To check the signal quality, you would need a high speed (>= 1 GHz) oscilloscope and a differential probe, if possible. Also with a single ended active probe, the signal quality could be checked roughly. Otherwise, ADS5474 sampling clock could be decreased as far as 20 MHz for test purposes, don't know if this can be achieved easily with the eval board.
Added after 9 minutes:
P.S.: A SERDES would normally be used with serialized LVDS data only, but with some FPGA families, it has to be connected when LVDS IO standard is used, although no deserialization is intended. It should work as you did.