rafimiet
Member level 5
I am working on image compression algorithm on VHDL and I have written a code for the same. The code is synthesize-able and simulate-able. The simulation results seem to me just fine.
Now I have a few difficulties:
1. I have to verify it in real-time and I have Artix-7 FPGA board (Digilant).
2. I don't know how to provide to it real-time image data; what are the different methods and related hardware?
3. How to display the output; different methods and hardware involved?
4. How to interface the same?
It will be very appreciable if anyone answers.
Regards
Mohammad Rafi
Now I have a few difficulties:
1. I have to verify it in real-time and I have Artix-7 FPGA board (Digilant).
2. I don't know how to provide to it real-time image data; what are the different methods and related hardware?
3. How to display the output; different methods and hardware involved?
4. How to interface the same?
It will be very appreciable if anyone answers.
Regards
Mohammad Rafi