Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Interface Verilog Custom Core To Read and Write From DDR RAM

Status
Not open for further replies.

aibk01

Newbie level 1
Joined
Jun 21, 2011
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,289
I want to add a custom verilog core to an already established pipeline of microblaze. The core should be able to read data from memory locations from DDR RAM (external) which is already present on PLB, process it i.e add to value of data and replace the data it has read with the new processed data. In short i want to add certain constant number to data on RAM in a parallel fashion,(video frame) and write back to those very locations.

Please guide me how should i go about. Should i create a custom peripheral?

Should i use FSL?

As i am new in this field kindly guide me!

Thank You


I am using Xilinx Spartan3E 1600.

With ISE and XPS 10.1 sp1
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top