You shouldnt come here with so many questions that follow the same general pattern "I dont understand - someone do my work for me". You should try to get things working and then construct questions that a specific.
Anyway, before we move on to why it doesnt work, lets fix some VHDL/digital logic knowledge gaps you appear to have:
1.
process (rst,clk,rw,cam_vsync,cam_href,cam_pclk)
You dont need all these signals in the sensitivity list, you only need clock and reset as its a sync process with an async reset,
2. You shouldnt place signal assignments outside of the clock branch. If you expect them to be async logic, they should be placed outside the process.
3.
crst1<= not crst1 after 100 us;
This will not work on real hardware. "after" statements are ONLY for simulation purposes, so it will be removed when synthesised, and in this case will create a logic loop, and will probably oscilate at very high frequency. You need to put in a counter and comparitor that works out when the 100 us is up, based on the counter clock.
4. the i signal is a 32 bit signal, completly unessesary. It wil also be always less than 13, because you initialise it to 13 and never reset it to anything, so just goes negative.
I highly suggest you read up on VHDL and digital logic, and then come back with more specific questions.