This is another obvious example why VHDL really sucks.
For netlist, you must treat it as real hardware. For a real hardware, there can not be any of this kind of fancy data structure. I think so, and all the tools think so...that's why you will get nothing but one array. (in verilog netlist, you will get (3:0) )
It's always a big problem with VHDL when doing gatelevel simulation, especially when you code your input/output port in such a way. No tools can maintain the same structure when it comes to netlist.
Now you can imagine if you try to do RTL to gate formal verification, how painful it is when you have this kind of thing. Even the port name will drive you crazy, let alone all those internal registers which you use bus.req , bus.data , ....bluh bluh bluh...
Still don't know why people still stick to VHDL.
Sorry....couldn't help.....