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interesting doubt - array type

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Junior Member level 3
Mar 23, 2002
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hello everybody

i am facing a problem with type array of array. below
i have given a simplified version of the problem

--package my_pak
type my_typ1 is array (0 to 1) of std_logic;
type my_typ2 is array (0 to 1) of my_typ1;

--entity declaration
use work.my_pak.all;

entity ....
out_put : out my_typ2;
end entity;

the problem here is, after synthesis, the generated
netlist is having port in this manner.

out_put : std_logic_vector(3 downto 0);

can anybody clear me as to in which manner the port
bits are rearranged. and another thing is one
synthesis tools has the port as (3 downto 0) and
another has it as (0 to 3). can we some how over ride
so that we can have the port in same manner as that of
original code so that the same test bench can be used
without any modification.

with warm regards,

This is another obvious example why VHDL really sucks.

For netlist, you must treat it as real hardware. For a real hardware, there can not be any of this kind of fancy data structure. I think so, and all the tools think so...that's why you will get nothing but one array. (in verilog netlist, you will get (3:0) )

It's always a big problem with VHDL when doing gatelevel simulation, especially when you code your input/output port in such a way. No tools can maintain the same structure when it comes to netlist.

Now you can imagine if you try to do RTL to gate formal verification, how painful it is when you have this kind of thing. Even the port name will drive you crazy, let alone all those internal registers which you use bus.req , , ....bluh bluh bluh...

Still don't know why people still stick to VHDL.

Sorry....couldn't help.....

hi stevepre

after trying for Synplicity and FPGA express, i gave a try for synopsis DA. Interestingly i found that by setting one of the below variable(i don't know exactly which one) we can get the port in the way in it was in the original code.

vhdlout_preserve_hierarchical_types = "USER";
vhdlout_single_bit = "USER";

so i think it is not the problem with the VHDL but with the tool we are using. by setting some option in Synplicity and FPGA express i hope we can get the desired result.

i will be very greatfull if any experts who have used these tools tell me what options to set


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