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interconnect parasitics estimation

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analog2003

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interconnect parasitics

Hi all,

I am designing a CMOS inverter, for which i need to estimate the interconnect parasitics prior to the layout-phase so i can estimate the delay. But, I was wondering how I could determine the dimensions of the interconnect in the design phase itself.

Thanks for your help in advance.
 

erikl

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analog2003 said:
I am designing a CMOS inverter, for which i need to estimate the interconnect parasitics prior to the layout-phase so i can accurately estimate the delay. But, I was wondering how I could determine the dimensions of the interconnect in the design phase itself.
accurately estimate is a wooden iron (Sideroxylon or oxymoron), s. http://en.wikipedia.org/wiki/Wooden_iron, and it needs a jolly nice job to achieve this! Guess you're the only one to want this done?!

No :D now: For a rough estimation, just double the input and output capacitances (or use dummy inverters at both the input and output). For a more accurate calculation, you'd have to draw the inverter and its route connections, measure their geometrical values and calculate their parasitic capacitances using the physical capacitance values (area & perimeter dependent) of the used wire layer(s) published in your PDK doc - or - much easier and more accurate: use the dedicated extract tool ;-)
 

analog2003

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Thanks, for pointing out that one. 'estimation' by itself means rough calculation, so I guess 'accurate estimation' should make no sense!
Also, thanks for the ideas.
 

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