Interchange NMOS and PMOS in CMOS

[varma844]

Hi ,

The normal CMOS acts as an inverter ....
What happens if the NMOS and PMOS are changed theier positions in CMOS ???
How would the circuit behave ??

Thanks

 

[itsthepip]

Hi,

If u interchange the roles of NMOS and PMOS , then NMOS would be connected to the supply and PMOS would be connected to the ground .

In that case, if u apply a zero , then NMOS would be OFF and PMOS would be ON ....so the output will be tied to ground ....and ieffect, it will be a zero .

If u apply a one, then NMOS would conduct and PMOS would be OFF ..So the output would be pulled up to the supply voltage ....U will get a one in this case...

If u observe both the cases , a zero at the input is giving rise to zero at the output...Similarly, a one at the input gives a one a the output...This is the operaion of a buffer .......

 

[sengyee88]

If you connect them as inverter, they will not function as inverter. Both of them may turns on at the same time, hence drawing large amount of current.

Both transistor Vth will be higher, as Vsb≠0.

 

[varma844]

Thanks dude ...

But , when I tried this in MODELSIM and Cadence , I found a few discrepancies ..

1) 5V at the input gave 4.6Vat the output
2) 0V at input gave 0.7V at the output

Why is this difference coming ????

Added after 5 minutes:

Hi sengyee88
Can u please tell me more about what happens during the turn on and turn off process , i.e during the transient period....
If more current flows, does the NMOS or PMOS power disspiation be more than expected ??

 

[itsthepip]

Probably the difference might be due to the fact that PMOS conducts a zero easily and doesnot conduct one easily..
NMOS conducts one easily and doesnot conduct zero easily......

 

[strennor]

the voltage difference comes from the Vth.

when Vin=Vcc, the upper NMOS conducts, results the Drain voltage=Vcc-Vth

same thing happens to PMOS when Vin=0

 

[sengyee88]

But , when I tried this in MODELSIM and Cadence , I found a few discrepancies ..

1) 5V at the input gave 4.6Vat the output
2) 0V at input gave 0.7V at the output

Why is this difference coming ????

This is similar to transmission gate, where NMOS cant efficiently pass high voltage and PMOS cant efficiently pass low voltage.
For your case, when input is 5V, PMOS is off, NMOS is on. But NMOS cant pass the high voltage (5V) to output, in fact, it should be Vout=Vcc-Vth. Similarly, for PMOS.

A typical inverter consume current during its transitions, and these transitions is fast. With your transistor arrangement, the transition could be longer, hence in average, consume more current. If you ramp up input slowly in simulation, you may be able to see the difference.

 

[ycj]

Hi,

If u interchange the roles of NMOS and PMOS , then NMOS would be connected to the supply and PMOS would be connected to the ground .

In that case, if u apply a zero , then NMOS would be OFF and PMOS would be ON ....so the output will be tied to ground ....and ieffect, it will be a zero .

If u apply a one, then NMOS would conduct and PMOS would be OFF ..So the output would be pulled up to the supply voltage ....U will get a one in this case...

If u observe both the cases , a zero at the input is giving rise to zero at the output...Similarly, a one at the input gives a one a the output...This is the operaion of a buffer .......

True. You can take this circuit as source follower.

 

[suhas_shiv]

Probably the difference might be due to the fact that PMOS conducts a zero easily and doesnot conduct one easily..
NMOS conducts one easily and doesnot conduct zero easily......

I think its the other way round. NMOS passes clean '0' and a bad '1' while PMOS passes clean '1' and bad '0'.

Suhas

 

[itsthepip]

Sorry dude
I accpet it
NMOS passes zero easily and PMOS passes one easily..Sorry for the mistake guys

And thanks to suhas_shiv for pointing it .....

 

[wanily1983]

in the new circuit, the two transistor can conduct at the same time?

 

[cad_slvr]

Varma,

Did you observe the currents during the 5V and 0V inputs? The circuit usually acts as a current driver. If you can run the simulations, post your results.

It is also used to drive long global interconnects in circuits. The only drawback with the circuit is that, you really have to play with the width of the driver to get the output. And on the other end of the interconnect, you need to have current mirrors to catch the signal. I remember coming across a paper which did some circuit design in this way. If I can find it, I'll post it here.

 

[zenisle]

drive long global interconnects in circuits

 

[teteamigo]

Inverter CMOS->interchange PMOS &NMOS-> output stage class B

 

[manjav01]

look into following attachment