Integer range question in VHDL.

[kostbill]

Hello.

In VHDL, when I have an integer in a certain range, if we assign to this integer a number that is outside the range, what will happen?

For example, I have this:


signal counter : integer range 0 to 16;
in reset, I assign counter to 16.
and then, in a rising clock edge, I have:
counter <= counter - 1;

What will happen after counter reaches zero? It will stay to zero or will it go back to 16?

Thanks.

 

[TrickyDicky]

In VHDL terms, you will get a range error when you try and simulate it and your simulation will fail when counter is zero.

When synthesised, your integer will be represented by 5 bits because you specified you wanted 16 in the range (16 = 10000 in binary). No synthesisors will put range checking on the result, so when it reaches zero it will roll over to 31 (11111). So because you dont want roll-over mechanics, and you want synthesis results to match simulation, you will need to put bounds checking in the code:

process(clk)
begin
  if rising_edge(clk) then
    if counter = 0 then
      counter <= 16;
    else
      counter <= counter - 1;
   end if;
  end if;
end process;

 

[alexan_e]

if you simulate that you get an error if you go above 16 or below 0.
If you implement it in hardware then an integer 0-16 is translated in a std_logic_vector(4 downto 0) (because 16 is binary 10000).
If you go below 0 you will get 11111 which is decimal 31, if you go above 31 you will go to 0.

if you use an integer range 0 to 15 (or even range 0 to 11) both of these can only fit in a 4 bit std_logic_vector
so in both of them you would have 15 if you go below 0 and 0 if you go above 15

Alex

 

[kostbill]

But I am not getting any errors in the simulation.
In my code, when my counter reaches zero, I continue to decrease it, until another event comes and reset it to 16 again. It stays that way for many clock cycles.
In the simulation, when the counter is decreasing in the code, it stays zero. It does not give me errors.

This is the code:

elsif(counter > 0) then
counter <= counter - 1;
...
elsif(counter = 0) then
DATA_R <= shift_reg;
...
elsif a = '1' then -- Note here, that signal 'a', is not going to be '1' for many clock cycles after my counter reaches zero.
counter <= 16;

Any ides what this will do in synthesis? Will it roll back to 16?

Thanks.

 

[alexan_e]

elsif(counter > 0) then
counter <= counter - 1;

in the above code you are preventing the counter to go below 0

Any ides what this will do in synthesis? Will it roll back to 16?.

As we said in the previous answers what you have defined using an integer of 16 is a 5 bit std_logic_vector, even if you remove the above if condition you will roll to 31. (from 00000 to binary 11111)
If you can declare it with range up to 15 then you will roll over to 15 (from 0000 to 1111)

Alex

 

[kostbill]

Silly me!!!

Thanks for the answer!