The port names should be identical in the definition as well as the instantiation. Your definition has ports a,b,s &c. But your instantiation has different ports(w1,w2,a,b) and (w2,w3,sum & cin).
The port names should be identical in the definition as well as the instantiation. Your definition has ports a,b,s &c. But your instantiation has different ports(w1,w2,a,b) and (w2,w3,sum & cin).
Verilog instances have sub module ports names after . and in parentheses the connection name is specified. You have just reversed that order.
And yeah, in simulation when you compile a code it will only check for syntax errors. This kind of errors are found at elaboration step. May be you have just tried the compilation of your code that's why you didn't get any error.