# Instiating submodules in verilog

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#### QMA

##### Member level 4
Dear all
I am new to verilog. I have written the below code for full adder using two half adders. it is giving me syntax error
"Can not find port w2 on this module"
Code:
module Full_adder(
input cin,
input a,
input b,
output cout,
output sum
);

wire w1,w2,w3;

.w1(c),
.a(a),
.b(b)
);

.w3(c),
.w2(w2),
.cin(cin));
or (cout,w1,w3);

endmodule

Code:
module H_adder(
input a,
input b,
output s,
output c
);

assign s = a^b;
assign c = a&b;

endmodule

#### sharath666

The port names should be identical in the definition as well as the instantiation. Your definition has ports a,b,s &c. But your instantiation has different ports(w1,w2,a,b) and (w2,w3,sum & cin).

##### Super Moderator
Staff member
You use the following format.

Code:
.sub_module_port_name (signal_name)

V
Points: 2

#### QMA

##### Member level 4
The port names should be identical in the definition as well as the instantiation. Your definition has ports a,b,s &c. But your instantiation has different ports(w1,w2,a,b) and (w2,w3,sum & cin).

it is not giving me error for the other ports like for w1, w3 or cin etc. i am not getting it actually.

- - - Updated - - -

You use the following format.

Code:
.sub_module_port_name (signal_name)

bundle of thanks dear. it has worked

#### MSBR

##### Member level 1
Verilog instances have sub module ports names after . and in parentheses the connection name is specified. You have just reversed that order.

And yeah, in simulation when you compile a code it will only check for syntax errors. This kind of errors are found at elaboration step. May be you have just tried the compilation of your code that's why you didn't get any error.

Hope that helps.

MSBR

#### dehati

##### Member level 3
See this complete working example here - basically there were two sets of issues in the code.

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