Instantiation problem

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swapnashah

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hi all,
how can i make a top module in verilog code?
it means dat two modules are instatiated in top module and i am giving input to a first module and output of dat module should goes into the input of the second module.
the final output should be from the second module.
pls help me out...
thanx in advance.
 

let your top module has input m and out put n.......

let say x and y be your two modules.

x(a,b);
y(p,q);

let say inputs a,p;
outputs b,q;
then

//instantiation
x mod1(.a(a1),.b(b1));
y mod2(.p(p1),.q(q1));

then

a1=m; //top module input to first module
p1=b1; //as out put of first module is in put to second module
n=q1; //as second module out put is your top module out put
 

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