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[SOLVED] instantiating verilog module in vhdl

Thread starter ramesh.balaram
Start date Dec 14, 2009

Status: Not open for further replies.

Dec 14, 2009

#1

R

ramesh.balaram

Newbie level 4

how to use a xilinx unisim library component written in verilog, in a vhdl top level code

how to perform the port mapping

Dec 14, 2009

#2

FvM

Super Moderator

Staff member

It's treated on the VHDL side like a VHDL component. Write a component defintion with the respective ports and instantiate it.

Status: Not open for further replies.

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