Hi,
In @ltera we instantiate a PLL, LVDS tx rx block using Megawizard Plugin Manager.
How i do it in Xilinx ISE ?
Also please tell me what is better Stratix or Virtex II pro ?
In my option, the Xilinx provide better document and more fast device than Altera. But it is also more expensive that Altera's device.
Both Stratix and V2p can fill the reqirment in application.
The difference in speed only need to be taken care of when your chip usage is very high.
always @(posedge pixel_clock)
begin
// this is not working
pixel_counter=pixel_counter+1;
// this is working
pixel_counter=325;
end
endmodule
Can't I increment a reg? I was doing this with M@X plus of @lter@. I use M0delsim for simulation and pixel_counter looks Hi-Z/undefined at simulation. What do I have to do?
Is there a step-by-step beginner to advanced book/ebook for X|linx I5E?