Instantiate same entity twice

[therealpaulie]

Hi all,

I have a dual port RAM. Two inputs and two outputs. The RAM is a entity.

Ok. I want to access (R/W) port A in the processing module and port B in the communication (RS232-serial) module. The idea is that I don't want to build a memory module that have DataInA, DataOutA, AddrA, DataInB, DataOutB, AddrB. (actually I have several RAMs and it doesn't look practical to have 30 outputs and 30 inputs for an RAM module).

How could I break one RAM in two so is once instantiate in module #1 (only the port A related signals) and once in module #2 (only the port B related signals).

Can you also recommend which is a good way to deal with double port RAM?

Thanks,
Paul

 

[TrickyDicky]

You cannot do what you are saying. The memory is 1 physical thing and so cannot be "broken" in two. You have to route your signals into one entity.

Also, any ports you dont want to use, just connect them to '0' or '1' or something. if you only ever read from Port A, tie the write enable to '0' for example.

 

[therealpaulie]

Hi,

I understand what you say. But how could I organize everything in a structure like in the attachement.

In the memory module there are several RAM blocks (can be more than 10 - I want to read in parallel, with one clock, more value stored in RAM) so the number of ports to RS232 is 50 and to Process Block also 50. I found it not practical to build up an entity with 100 ports !!!. But in the same size I would like to keep my code clean and the entire structure (of files and hierarchy) nice organized.


Thank,
Paul

 

[TrickyDicky]

Memory modules has to be its own entity. And then you connect the ports to the RS232 and Process Module. There is no other way to do it.

 

[permute]

array types might be of interest. if you actually have 50 inputs and 50 outputs, then there isn't too much you can do for the instantiation. You can use arrays types as inputs, eg: type my_array_type is array (natural range <>) of std_logic_vector(7 downto 0); If this type is defined in a package, then it can easily be used as a port -- data_in : my_array_type(NUM-1 downto 0); where NUM is an integer generic.

Generates would also be useful to generate the rams based upon NUM.