Inputs to a VHDL entity

[shaiko]

Hello,

As a design methodology, would it be wise to register ALL inputs to a VHDL entity?
I don't mean only the entities that are inputs to the FPGA...but ALL inputs to ALL entities (except those that require zero latency for some reason).

To make a design in wich ANY input port to ANY entity is registered.

 

[TrickyDicky]

Inputs to the chip should be registered. But if you then pass the output of the register down 10 layers of heirarchy, you'll be going through 10 entities with what is just a wire (and it could be a really short wire - the heirarchy has nothing to do with the final routing), so they dont all need to be registered going into every single entity.

It wont hurt having them all registered though. just add latency (which may be unneccesary).

If you're developing a peice of IP that someone else may be using, it might be sensible to register the inputs at the top level at least, just incase the other user forgot to register his outputs.
So register all outputs.

 

[shaiko]

Thanks for the advice!

What about outputs?
Should we register after every time we pass a complex combinatorical circuit?

 

[FvM]

You should at least place pipeline registers, if timing closure can't be achieved otherwise.

 

[shaiko]

I take it as a yes...
Usually, at the time I write the code I don't even know what the target device will be,
This makes timing analysis harder.

When designing logic on an FPGA (not custom ASICs),
can you think of a "rule of thump" for how many combinatorical levels can be passed before it's advisable to reregister the signal?
(for speed lower than 200 Mhz).

 

[TrickyDicky]

it will really depend on the chip (and clock speed)
Newer devices will probably be quite a few luts. older ones not so many. you'll have to see from the timing analysis.

 

[FvM]

With recent FPGA families, a LUT level involves e.g. 0.2 or 0.3 ns. So a lot of them can be cascaded between registers. The problem is however with complex logic, e.g. for arithmetic expressions. You'll find typical performance numbers for these complex units in FPGA data sheets.