If I get it right, you mean the change in offset voltage in the input signal changes the gate biasing voltage of the NMOS transister and then changes the output impedance, right?
However in my circuit, there is on-chip DC blocking cap in the between the signal source port and the gate of the transistor. Also right after the cap, there is a DC biasing terminal controlling the biasing voltage of the gate. So in this case, no matter what DC offset voltage it is in the RF input signal, it should not affect the gate biasing voltage. Then how come does the output impedance change?
I was thinking that there might be a leakage current through the DC blocking cap (10pF) since it's on-chip cap. But I am not sure.