Input DC offset voltage changes output impedance of a Class E PA?

[sharethewell]

Hi. I am simulating a Class E power amplifier in Cadence Virtuoso Spectre. What I found interesting about the output impedance is that it changes according to the input DC offset voltage. Here is what I found:

Two types of input signals:

A. DC(0.69V)+AC sine (433MHz)
B. Pure AC sine (433MHz)

When I simulated the output impedance of the PA with PSS+PSP analysis. I got different impedance reading from two different input signals.

Do you know why? I can't figure out how DC voltage will change the output impedance.Thanks.

 

[BigBoss]

It's normal..
Output impedance is operating point dependent parameter of an active device.
Intrinsic capacitors are indeed variable capacitors with applied voltage between-for instance- drain and substrate and that's why they are Vds dependent.
Similarly, Instrinsic output resistance is not a fixed resistance instead a variable resistance depediing on drain current and bias voltages.. so on..
So, briefly the terminal impdances are not fixed, bias dependent and frequecy dependent components.

 

[sharethewell]

It's normal..
Output impedance is operating point dependent parameter of an active device.
Intrinsic capacitors are indeed variable capacitors with applied voltage between-for instance- drain and substrate and that's why they are Vds dependent.
Similarly, Instrinsic output resistance is not a fixed resistance instead a variable resistance depediing on drain current and bias voltages.. so on..
So, briefly the terminal impdances are not fixed, bias dependent and frequecy dependent components.

If I get it right, you mean the change in offset voltage in the input signal changes the gate biasing voltage of the NMOS transister and then changes the output impedance, right?

However in my circuit, there is on-chip DC blocking cap in the between the signal source port and the gate of the transistor. Also right after the cap, there is a DC biasing terminal controlling the biasing voltage of the gate. So in this case, no matter what DC offset voltage it is in the RF input signal, it should not affect the gate biasing voltage. Then how come does the output impedance change?

I was thinking that there might be a leakage current through the DC blocking cap (10pF) since it's on-chip cap. But I am not sure.

 

[BigBoss]

If I get it right, you mean the change in offset voltage in the input signal changes the gate biasing voltage of the NMOS transister and then changes the output impedance, right?

However in my circuit, there is on-chip DC blocking cap in the between the signal source port and the gate of the transistor. Also right after the cap, there is a DC biasing terminal controlling the biasing voltage of the gate. So in this case, no matter what DC offset voltage it is in the RF input signal, it should not affect the gate biasing voltage. Then how come does the output impedance change?

I was thinking that there might be a leakage current through the DC blocking cap (10pF) since it's on-chip cap. But I am not sure.

Even you use DC blocking capacitor, the RF signal may have a DC component because of assymetric signal shape.If this signal is coming from another amplifier, this generally happens.But that signal should have large amplitude and must be pretty distorted.
Another tough can be a leakage current through gate but this pehnomena is seen with GaAs FET and relative components such as pHEMT etc. Because at the gate there is a Schottky diode and and that diode has a leakage current increasing with RF signal and temperature.Consequently, this current changes the bias point of the FET.

There may be other toughts but I don't know which process you have used that's why I cannot say a concrete thing..