Dec 15, 2018 #1 A Alauddin123 Newbie level 5 Joined Mar 24, 2016 Messages 9 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 89 Hi All, I have been working on FPGAs and know that how important I/O delays are in order for the device to work in external environment . But to assign its value i have found like some people prefer input delay as 75% of clk_period and output delay as 25%. What is actuall logic behind this ? can any one explain. If this values doesn't make any sense then what is the general way of assigning the values ?
Hi All, I have been working on FPGAs and know that how important I/O delays are in order for the device to work in external environment . But to assign its value i have found like some people prefer input delay as 75% of clk_period and output delay as 25%. What is actuall logic behind this ? can any one explain. If this values doesn't make any sense then what is the general way of assigning the values ?
Dec 15, 2018 #2 A Akanimo Advanced Member level 3 Joined Aug 30, 2016 Messages 848 Helped 145 Reputation 290 Reaction score 165 Trophy points 1,323 Activity points 7,123 These particular delays basically have to do with external components connected to the I/O pins and also those caused by the traces that connect them. The delay values are extracted from the datasheet of the ICs interfaced with the FPGA and of course adding that of the connecting trace.
These particular delays basically have to do with external components connected to the I/O pins and also those caused by the traces that connect them. The delay values are extracted from the datasheet of the ICs interfaced with the FPGA and of course adding that of the connecting trace.